Historically, design engineers implementing high-speed interfaces have met numerous challenges in maintaining interface signal timing relationships and signal quality. Issues such as skew, jitter, crosstalk, and noise have been addressed through a combination of analog circuitry and board/chip physical design rules. Generally, analog circuitry has been used for signal conditioning, filtering, impedance matching, and noise suppression, while physical design rules have targeted skew and crosstalk minimization.
Hybrid parallel-serial interfaces that leverage high-speed serial links have evolved out of the need to scale bus bandwidth, while containing interface electrical and physical design challenges. Commonly, the transition to serial and parallel-serial interfaces has been accompanied by an increase in design complexity caused by a loss of signal-to-signal timing relationships. Using hybrid parallel-serial interfaces may eliminate notions of setup, hold, and fixed skew times at the interface, rendering static timing at the interface relatively insignificant.
Various approaches have been tried for functional verification of uncertainty in edge placement, programmability of signal delay, and skew over a wide range of values, variable timing relationships between channels, and an ability to vary timing parameters across and outside of the valid range.
Thus, it is with respect to these considerations and others that the present invention has been made.